Field of Invention
The present invention relates to a high voltage Metal Oxide Semiconductor (MOS) device; particularly it relates to a MOS device having a reduced unit pitch in the layout. The present invention also relates to a manufacturing method of the MOS device.
Description of Related Art
FIGS. 1A and 1B show a top view and a cross sectional view of a prior art high voltage MOS device (N type high voltage MOS device 1) respectively. As shown in FIGS. 1A and 1B, the high voltage MOS device 1 is formed in a semiconductor substrate 11, wherein along the vertical direction, the semiconductor substrate 11 has an upper surface 11′ and a bottom surface 11″ opposite to the top surface 11′. The high voltage MOS device 1 comprises an N type well region 12, a P type body region 16, a gate 13, an N type source 14, an N type drain region 17, and a P type body contact region 18. The N type source is formed in the P type body region 16, and the P type body contact region 18 is formed in the P type body region 16. As shown in the figures, the N type source 14 and the P type body contact region 18 are typically parallel to the gate 13 in the width direction, wherein the N type source 14 neighbors the gate 13, and the P type body contact region 18 does or does not contact the N type source 14, and typically does not contact the gate 13.
The prior art shown in in FIGS. 1A and 1B has the following drawback. When plural N type high voltage MOS devices 1 shown in FIGS. 1A and 1B form a switch array (for example, at the left side of the N type MOS device 1 of FIG. 1A, another high voltage MOS device which has the same layout but in a mirrored arrangement as the N type MOS device 1 is formed and connected with the N type MOS device 1 in parallel, and the two devices share the N type source 14 and the P body contact region 18), the unit pitch D of this prior art N type MOS device 1 is large, so the resistance per unit area of the N type high voltage device 1 is large, and therefore the manufacturing cost is high and the device performance is low.
Compared to the prior art of FIGS. 1A and 1B, the high voltage MOS device according to the present invention has a smaller unit pitch, so the resistance per unit area is smaller, or the operating voltage can be higher under the same unit area. Therefore, the present invention has a lower cost, better performance, and broader application range.